1. Field of the Invention
The present invention relates to semiconductor memory devices and more particularly to a structure of a semiconductor memory device capable of attaining higher speed data reading and writing operations
2. Description of the Background Art
Due to the recent demand for higher speed and larger capacity semiconductor memory devices, there is a need to increase the data capacity that can be handled in unit time.
In order to attain higher speed data reading and writing operations, it is necessary to cause data lines (hereinafter, signal lines that transmit storage data having two states of H and L levels are collectively referred to as data lines), which tend to have larger parasitic capacitance due to their design and operate slowly as a result, to operate at high speed. Accordingly, such a method of attaining higher speed reading and writing operations is generally adopted that is intended to shorten the time necessary to charge and discharge a data line by transmitting storage data after setting in advance the potential of the data line to an intermediate value of the potentials (hereinafter, referred to as an intermediate potential) corresponding to the two logical levels of the storage data.
The above described data line is often provided as a pair of complementary lines. Since the complementarily provided lines of the data line pair have almost equal parasitic capacitance and receive data having their logical levels inverted from each other, the both lines can be set to an equal potential (that is, an intermediate potential) by simply short-circuiting them (hereinafter, the operation of setting the potential of a data line at a prescribed value by short-circuiting a data line and another data line or the like is generally referred to as an equalization operation).
The equalization operation of such a data line pair provided as complementary lines is described, for example, in Japanese Patent Laying-Open Nos. 60-242585 and 06-342597.
One specific example of attaining higher speed data reading and writing operations is the method of sequentially changing only column addresses while the same row address is selected thereby attaining higher speed column accessing. In this case as well, the operation speed is made much higher by waiting for data line selection after equalizing in advance an input/output signal line, to which data is read, in response to an address transition detection signal (hereinafter, referred to as an ATD signal) that is produced by an address transition detection circuit (ATD; Address Transition Detector) when the circuit detects transition of external input addresses.
Since the equalization operation is a useful technique for attaining an higher speed operation as described above, it may be necessary that even data line that is not complementarily provided has its data line potential set to a prescribed intermediate potential, prior to transmission of storage data, by applying the equalization operation. Equalization circuits having a structure as described below have conventionally been used in this case.
FIG. 10 is a circuit diagram showing a structure of an equalization circuit 260 in a conventional art (hereinafter, referred to as the first conventional art).
Referring to FIG. 10, the I/O line 80 and the data bus 90 representatively show two data lines that are directly connected from a group of hierarchically provided data lines. Equalization circuit 260 is provided to apply the equalization operation to data bus 90 in response to an equalization signal EQZ. I/O line 80 is connected to the output node of a sense amplifier for amplifying storage data in a memory cell in accordance with a column selection operation corresponding to a column address. A data bus driver (inverter) 70 inverts data on the I/O line and transmits it to data bus 90.
Since a global data line is generally larger in interconnection length and width, the parasitic capacitance Cl of I/O line 80 and the parasitic capacitance C2 of data bus 90 have the relationship of C2&gt;&gt;C1. In this case, it is important to carry out data transmission after data bus 90 having larger parasitic capacitance is set to a prescribed potential to attain a higher speed operation.
Equalization circuit 260 includes an n-channel transistor 261 receiving equalization signal EQZ at its gate and connecting I/O line 80 and data bus 90, and a p-channel transistor 262 receiving a signal /EQZ, as an inversion signal of EQZ, at its gate and connecting I/O line 80 and data bus 90. In response to activation of signal EQZ, equalization circuit 260 short-circuits I/O line 80 and data bus 90, each of which transmits data having an opposite state from each other, and sets data bus 90 to an intermediate potential.
FIG. 11 is a circuit diagram showing a structure of an equalization circuit 360 in another conventional art (hereinafter, referred to as the second conventional art). Since I/O line 80 and data bus 90 are the same as FIG. 8, the description thereof will not be repeated.
Referring to FIG. 11, equalization circuit 360 includes an n-channel transistor 361 receiving equalization signal EQZ at its gate and connecting data bus 90 and a Vcc power supply for supplying a potential (hereinafter, referred to as Vcc) corresponding to the H level of storage data, and a p-channel transistor 362 receiving signal /EQZ as an inversion signal of EQZ at its gate and connecting data bus 90 and a Vss power supply for supplying a potential (hereinafter, referred to as Vss) corresponding to the L level of storage data.
In response to activation of the equalization signal, equalization circuit 360 short-circuits the data bus, the Vcc power supplly and the Vss power supply, and sets the potential of data bus 90 to the vicinity of 1/2 Vcc.
However, parasitic capacitance C1 of I/O line 80 and parasitic capacitance C2 of data bus 80 are substantially different in equalization circuit 260 in the first conventional art. Accordingly, even when the I/O line and the data bus are connected by equalization circuit 260, the potential of data bus 90 cannot be set to the vicinity of 1/2 Vcc, and the higher operation speed cannot fully be attained.
In equalization circuit 360 in the second conventional art, data bus 90 can be set to the potential in the vicinity of 1/2 Vcc by short-circuiting data bus 90 between the Vcc power supply and the Vss power supply. However, a current flows through the path from Vcc power supply, to n-channel transistor 361, to p-channel transistor 362, and then to the Vss power supply during the equalization operation, and thus unnecessary power loss is caused.